open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists
// readme
Takahe
Hardware synthesis. SystemVerilog, VHDL and ABEL-HDL in, gate-level netlists mapped to real foundry cells out.
PicoRV32, a complete RISC-V CPU core, synthesises to 3,305 SKY130 gate instances with zero parse errors and zero multi-driver nets. Five processors have been through OpenROAD.
Named after the takahē (Porphyrio hochstetteri, also pronounced as Tah-Kah-Hey), declared extinct in 1898 and rediscovered alive in the Murchison Mountains in 1948.
This project started so I could learn how to make my own chips and understand Verilog better. I also wanted to do more historical reconstructions of old computers, which hopefully explains why it’s built the way it is.
What It Does
# Binary synthesis to SKY130 130nm
./takahe --lib sky130.lib --map counter.v design.sv
# VHDL
./takahe --vhdl --parse design.vhd
# ABEL-HDL (PLD designs from the 1980s-2000s)
./takahe --parse decoder.abl
# Ternary synthesis (balanced ternary, à la Setun)
./takahe --radix 3 --opt --parse design.sv
Four PDK Targets
| PDK | Node | Status |
|---|---|---|
| SKY130 | 130nm | Fully supported, five processors synthesised through OpenROAD |
| IHP SG13G2 | 130nm BiCMOS | … |