UHDM to RTLIL Frontend

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A Yosys frontend that enables SystemVerilog synthesis through UHDM (Universal Hardware Data Model) by converting UHDM representations to Yosys RTLIL (Register Transfer Level Intermediate Language). Focused on creating post-synthesis (Gate-level) netlists that matches RTL simulation using Verilator as the golden standard.

✅ Every result is verified

Nothing here is counted as “working” on a read-only or vacuous pass. Every synthesized netlist is proven correct by formal equivalence — Yosys equiv_induct plus a sound SAT-from-reset miter against the Yosys Verilog-frontend golden — and/or by high-activity randomized Verilator co-simulation against the original RTL. A SAT miter also adjudicates every divergence so an inductive-proof gap is never mistaken for a real bug. See Verification Methodology below.

Overview

This project bridges the gap between SystemVerilog source code and Yosys synthesis by leveraging two key components:

1.…