Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass. Highest ranking complex SystemVerilog 2 functional gate-level netlist flow for Yosys compilation
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UHDM to RTLIL Frontend
A Yosys frontend that enables SystemVerilog synthesis through UHDM (Universal Hardware Data Model) by converting UHDM representations to Yosys RTLIL (Register Transfer Level Intermediate Language).
✅ Every result is verified
Nothing here is counted as “working” on a read-only or vacuous pass. Every synthesized netlist is proven correct by formal equivalence — Yosys
equiv_inductplus a sound SAT-from-reset miter against the Yosys Verilog-frontend golden — and/or by high-activity randomized Verilator co-simulation against the original RTL. A SAT miter also adjudicates every divergence so an inductive-proof gap is never mistaken for a real bug. See Verification Methodology below.
Overview
This project bridges the gap between SystemVerilog source code and Yosys synthesis by leveraging two key components:
- Surelog - Parses SystemVerilog and generates UHDM
- UHDM Frontend - Converts UHDM to Yosys RTLIL
This enables full SystemVerilog synthesis capability in Yosys, including advanced features not available in Yosys’s built-in Verilog frontend.